To transmit a continuous data stream over a packet-oriented communication network, the data stream is first split into data packets for individual transmission which are each provided with a destination address and a timestamp. On exiting the packet-oriented communication network the data packets are reassembled into a continuous data stream. Being transmitted in the packet-oriented communication network basically mutually independently, the data packets generally do not arrive at their exit point at equidistant intervals or, frequently, in their original sequence. To balance out these variations in propagation time, before the data stream is assembled the data packets, or their data content, are usually intermediately stored in what is called a jitter buffer, from which they are read out at constant intervals. In this way it is possible to reconstruct a continuous data stream from data packets arriving at irregular intervals.
A disadvantage of a jitter buffer of this type is that the transmission of data is further delayed owing to buffering. The average time the data packets spend in the buffer should therefore be kept to a minimum. However, it must also be ensured that the average buffering time is not selected to be too short as that would prevent data packets which arrive late from being arranged within the time sequence for output from the jitter buffer. If a data packet arrives after a data packet which followed it in the original transmission sequence has already been fed out from the jitter buffer, the regular output time for the data packet arriving late will have elapsed and that data packet will have to be rejected. An aim of jitter buffer regulation is accordingly to minimize the average buffering time allowing for the ancillary condition of a rate of data packet loss which is still acceptable.
The practice to date for regulating a jitter buffer has been to measure the mean transmission delay due to buffering and to adjust it to a desired delay by means of a first regulating circuit. The desired delay can either be pre-specified and fixed or regulated by a second regulating circuit in such a way that the transmission delay is minimized while maintaining a rate of packet loss which is still acceptable. However, specifying a fixed desired delay limits the flexibility of jitter buffer regulation, while additionally regulating the desired delay has the disadvantage of requiring a second regulating circuit. Regulation is made substantially more complex by two, mutually influencing regulating circuits, and problems with stability may also arise.